Vertical stacking of multiple flip chips in stacked die packages is frequently used in the semiconductor manufacturing. Such method requires chips to be processed with through silicon interconnects to enable electrical connection between the stacked chips. The through silicon interconnects may typically be formed by creating vias that extend from the inactive or backside of the chip to the active or front side of the chip, and subsequently filling the vias with a conductive material such as copper.
The stacking may be performed at the wafer level in which the through silicon interconnects are formed on a plurality of wafers, and the plurality of wafers are stacked to form a wafer stack. The wafer stack may be singulated into individual units which can be further processed (i.e., mounting onto a substrate, molding and solder ball mounting) to form a semiconductor package. However, a disadvantage of such a method is that some of the dies in the wafer stack may be defective, thereby resulting in packages with defective dies.
There is therefore a desire to provide an efficient method of forming stacked die packages having known good dies.